Su saati ve dead reckoningTarih kitaplarını okurken “Saat …’de buluşalım.” cümlesinin insanlık lügatına çok yakında girdiğini farkettim. 300.000 yıllık insanlık…Oct 3, 2021Oct 3, 2021
Cache Control of e500mc at runtimeHi. In this story I want to explore cache control details at e500mc core and share it with you.Jul 5, 2021Jul 5, 2021
VxWorks Boot Sequence NotesAt a minimum, initializing a processor consists of providing a portion of code, and possibly some tables, that are located at the specific…Jan 3, 2021Jan 3, 2021
Dynamic Time WarpingWe may start learning DTW(Dynamic Time Warping) with understanding what is time series. According to Wikipedia, a time series is a series…Sep 28, 2020Sep 28, 2020
Type Checking in JavaType checking is the process of verifying and enforcing the constraints of types, and it can occur either at compile time (i.e…Aug 8, 2020Aug 8, 2020
ANTLR in VSCode without import errorAt first step you should install Java Extension Pack by Windows.Jun 27, 20201Jun 27, 20201
Power Control of ZC702 with PMBusThe ZC702 board uses power regulators and a PMBus compliant system controller from Texas Instruments to supply core and auxiliary voltages…May 8, 20201May 8, 20201
PDB Link2019 Errors on Visual Studio while DebuggingI just created “Empty C++ Project” and I added new main.cpp and showed main function as an entry point. But when I hit the F5 debug button…Jan 31, 2020Jan 31, 2020
Row-major or column-major order?Difference between two program is in 12th row. Typically, caches are designed so that if a value is read in from memory, that value, plus…Oct 22, 2019Oct 22, 2019
LLVM PassThis text is cop ied entirely from https://www.cs.cornell.edu/~asampson/blog/llvm.htmlSep 18, 2019Sep 18, 2019
